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 | THURSDAY, June 10, 2004, 09:00 AM - 12:00 PM | Room: 11
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| | HoT Structured ASICs
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| | Physical Design of Structured ASICs - ViASIC, Inc.
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| | Organizer(s): John Maushammer
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| |  The tutorial will begin with an in-depth exploration of two major classes of structured ASIC architectures: via-programmed and metal-programmed. Participants will learn how these architectures work and the advantages and disadvantages of each, with an emphasis on comparing masks costs, real-world density, design flows, time to market and the yield and signal integrity advantages that come with architectural regularity. We will also review footprint selection, foundry process and other technical design considerations, while looking at the forces driving the rapid adoption of structured ASICs.
Participants will take a real design through the complete design flow, from RTL to tape-out, as they build a via-programmed structured ASIC using leading tools and technologies. Get hands-on experience with the ViaMask 0.13 library and the ViaPath physical implementation tool while performing placement, memory generation, and routing; investigate strategies and techniques for insertion of test, clock and power. The tutorial will also feature a review of the design flow for metal-programmed structured ASICs using physical synthesis and ViASIC's metal routing engine.
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